Those skilled in the art are familiar with the design and implementation of driver circuits utilizing an NMOS power transistor in a high-side driver, low-side driver or half-bridge driver topology. For example, in a high-side implementation, the drain terminal of the NMOS power transistor is coupled to a supply voltage node and the source terminal of the NMOS power transistor is coupled to an output node to be driven. The gate terminal of the NMOS power transistor is coupled to receive a gate control signal whose voltage level controls the degree to which the NMOS transistor is turned on or off.
A number of common design requests are associated with the design of driver circuits such as: a) ensuring the lowest on-resistance for the NMOS transistor, the gate control signal needs to have a high voltage and it is desired that the voltage be accurate; b) in some dedicated applications, such as with the half-bridge topology applied as a motor driver, there may exist a need to limit the current at the output node; c) providing a built-in gate stress circuit to ensure robust operation of the driver circuit; d) controlling the gate-to-source voltage of the NMOS transistor needs in some conditions (such as with fast transients) use of a clamp circuit; and e) ensuring that the clamp circuit does not impact the gate stress test.
Addressing all of the foregoing common design requests has proven to be a difficult chore for the circuit designer. For example, if the circuit designer uses an inaccurate gate clamp, the clamp voltage will exhibit a wide operating voltage range due to temperature and process corner variation. Indeed, in some cases the variation may overlap into normal working range for the driver circuit and may extend past the absolute maximum rating (AMR) of the transistor device. If the designer instead chooses an accurate gate clamp, the circuit design becomes overly complex due, in part, to a need for implementing extra circuitry with extra bias current on the output. Still further, complex circuits are required to disconnect driver control circuitry from the gate terminal of the NMOS transistor and further to disconnect the clamp circuit during stress testing.
There is accordingly a need in the art for a driver circuit utilizing an NMOS power transistor with a gate clamp supporting both gate protection (clamp) during normal working mode and gate stress testing mode.